Generally, as the level of semiconductor device integration increases, it is desirable to refine a design rule for the semiconductor device to increase the operation speed of the device. However, as sizes of gate and source/drain electrodes of a metal oxide semiconductor (MOS) transistor are reduced accordingly, sheet resistance and contact resistance of the device increases. Previously, sheet and contact resistances were of little concern.
To solve this problem of increase sheet and contact resistances, a technology for forming a silicide of high fusion point metal with a low specific resistance in the gate electrode and the source/drain has been developed. As a result, a resistance of the gate electrode and a contact resistance of the source/drain were considerably reduced. In the past, the formation processes for silicide in the gate electrode and the source/drain were separately performed. The separation of these processes resulted in a complicated process having increased manufacturing costs. However, in the present, in consideration with a simplification of the manufacturing process and a cost reduction, a single formation process for silicide layer on the gate electrode and the source/drain, i.e., a Self Aligned Silicide (Salicide) process, was developed.
In the Salicide process, when a high fusion metal is deposited simultaneously on a silicon layer and an insulating layer and the high fusion metal is annealed, the high fusion metal on the silicon layer is reacted into a silicide through a silicide reaction whereas the high fusion metal on the insulating layer remains as it is without the silicide reaction. Then, the unreacted high fusion metal is removed, so that the silicide layer is left only on the silicon layer.
Meanwhile, in a non-salicide region for a resistance and an Electro-Static Discharge (ESD) shielding circuit of the semiconductor device, an insulating layer for preventing the deposition of high fusion metal is deposited.
The salicide process has been newly used for the formation process for silicide, instead of a conventional chemical vapor deposition (CVD) process that has been adapted to the manufacturing process for MOS transistor. Particularly, a titanium salicide process having an excellent characteristic for electric resistance of metal and for electric resistance of silicide had been adapted to the manufacturing process of MOS transistor.
According to the conventional method of manufacturing a semiconductor device, as shown in FIG. 1, an insulating layer for isolation (not shown) is formed on a field region (not shown) of a semiconductor substrate to define an active region of the semiconductor substrate 10, formed of such as, for example, a P type single crystal silicon material. Herein, the semiconductor substrate 10 is classified into a salicide region 11 and a non-salicide region 12.
Successively, a gate insulating layer 13 of MOS transistor is formed on the active region of the semiconductor substrate 10, and a pattern of a poly crystal silicon layer for a gate electrode 15 is formed on a gate electrode formation region of the gate insulating layer 13. Then, although not shown in the drawing, using the gate electrode 15 as a mask for the formation of a lightly doped drain (LDD) region, N type impurities, for example, phosphorous, are lightly ion-doped into the active region of the semiconductor substrate 10. Then, an insulating layer, for example, a spacer 17 of a nitride layer is formed on both sidewalls of the gate electrode 15. Successively, using the gate electrode 15 and the spacer 17 as an implantation mask, the impurities for the source/drain (not shown), for example, the N type impurities are heavily ion-doped into the active region of the semiconductor substrate 10.
Successively, to prevent the formation of silicide layer on the non-salicide region 12 upon the formation of silicide layer on the salicide region 11, an insulating layer is formed only on the non-salicide region 12. Explaining this with reference to FIGS. 2 and 3, an oxide layer 19 as a silicide shielding layer is deposited on the whole surface of the semiconductor substrate 10 to cover the gate electrode 15 and the spacer 17, by use of, for example, a low pressure TEOS CVD process. Then, a photoresist 21 to be used as an etching mask of the oxide layer 19 is formed on the oxide layer 19 of the non-salicide region 12. Thus, as shown in FIG. 3, using the photoresist 21 as an etching mask, the oxide layer 19 is isotropically etched by a wet etching process thus to expose an upper surface of the gate electrode 15 and also to leave the oxide layer 19 only on the non-salicide region 12. Herein, it is preferable that the oxide layer 19 is not left on an upper portion of the spacer 17 of the salicide region 11.
As shown in FIG. 4, the photoresist 21 is removed to expose the oxide layer 19 of the non-salicide region 12. Then, the N type impurities, for example, arsenic (As) ions, are implanted into the whole area of the semiconductor substrate 10 by using a Pre-Amorphization-Implant (PAI) process to easily perform a salicide process on the poly crystal silicon layer of the gate electrode 15.
As shown in FIG. 5, the surface of the semiconductor substrate 10 is cleaned by a cleaning solution such as dilute hydrogen fluoride (DHF), removing contaminants remaining in the surface of the semiconductor substrate 10. Then, using a sputtering process, a Ti/TiN layer 23 is deposited on the whole area of the semiconductor substrate 10.
As shown in FIG. 6, the Ti/TiN layer 23 is annealed. Herein, since the Ti/TiN layer 23 on the gate electrode 15 causes a salicide reaction, a silicide layer 25 is formed only on the gate electrode 15. Of course, although not shown in the drawing, the silicide layer is also formed on the source/drain of the salicide region 11. However, the Ti/TiN layer 23 on the other region does not cause a salicide reaction, so that the Ti/TiN layer 23 is left without reacting.
Finally, the unreacted Ti/TiN layer 23 is removed by wet-etching process, so that the silicide layer 25 is left only on the gate electrode 15.
However, in prior approaches, because the oxide layer 19 of the non-salicide region 12 is exposed, arsenic (As) ions are implanted into the oxide layer 19 of the non-salicide region 12 as well as the gate electrode 15, using the PAI process. As a result, the etching rate of the oxide layer 19 of the non-salicide region 12 is rather increased after the PAI process.
Accordingly, when the semiconductor substrate 10 is cleaned before the deposition of the Ti/TiN layer 23, the oxide layer 19 and the gate insulating layer 13 are completely etched on a part A of the non-salicide region 12, possibly exposing the active region of non-salicide region of the semiconductor substrate 10 beneath the oxide layer and the gate insulating layer.
In this state, if the salicide process is performed, the oxide layer 19 hardly serves as a silicide shielding layer, so that an unwanted silicide layer 27 may be formed on the part A of the non-salicide region 12 of the semiconductor substrate 10, which degrades an electric characteristic of the semiconductor device.